The present invention relates to an apparatus for testing semiconductor chips and to a semiconductor device.
With recent advances in the technology of CMOS ultra-miniaturization and in the technology of low-amplitude differential signal processing circuits, LSIs operating at speeds over 1 GHz, such as those compliant with the IEEE 1394b standard, have increased significantly in operating speed.
In the technology of testing an LSI which should assure the high-speed operation thereof, there is a case where the processing speed of the driver or comparator of an LSI tester is lower than the signal processing speed of the LSI. In that case, a test cannot be performed by using a normal method. No problem is encountered if the test is at the research stage. For mass production, however, a test which allows higher-speed processing speed becomes necessary.
As an example of a test method which allows higher-speed processing, there is one which uses a PLL circuit embedded in an LSI to test the LSI for high-speed transmission. To test an LSI for high-speed reception, there is another which uses a PLL circuit within the LSI in place of a circuit intended for a loop-back test or the like. The actual situation is that, to test an LSI which uses a high-speed differential transmission system as defined in the IEEE 1394 standard, a test is performed by particularly using a PLL circuit at a critical processing speed in terms of the performance of an LSI tester.
If the PLL circuit is used in a test as described above, the processing speed is increased compared with the case where the PLL circuit is not used. However, the time required for a locking period becomes about 1000-fold longer than in the case where the PLL circuit is not used. As the cause of the longer time required, the lowering of test stability due to the characteristics of the PLL circuit may be considered. FIG. 8 shows an example of the difference between an overall test time when the PLL circuit is used and an overall test time when the PLL circuit is not used. From FIG. 8, it will be understood that, if a test is performed by using the PLL circuit, the time required for an edge search, which is performed to assure test stability, is extremely long compared with the case where the PLL circuit is not used.
By thus using the PLL circuit to respond to a request for higher-speed processing during test, the test time is increased due to the lowered test stability and test cost is also increased disadvantageously.
If a low-spec LSI tester is used in the hope of increasing the processing speed and suppressing the lowering of test stability, the jitter accuracy, skew accuracy, resolution, voltage accuracy of the LSI tester are reduced considerably so that variation between different LSI testers presents a problem. This prevents indiscrete use of the low-spec LSI tester.